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It is natural, therefore, at high transfer rates, that times of transfer of incoming parallel data to the outputs of the parallel-to-parallel register coincide with loading times for this data at the outputs of the parallel-to-parallel register in the parallel-to-serial register. Since both registers are essentially designed with logic flip-flops, their operation depends on logic transition times (rising or falling edges) of the clock signals. The phasor is used to generate the first clock signal with a phase which is a function of the phase of the incoming parallel data. Indeed according to conventional embodiments, a phasor is provided in the converter to generate the first clock signal which rhythms the transfer of data outgoing from the parallel-to-parallel register whereas a time base in the converter provides the second clock signal independently of the first clock signal. slope, integral the characteristic being duration, interval, position, frequency, or sequenceĪccording to the prior art, the first and second clock signals having the same frequency are independent of each other in terms of phase. H03K5/26- Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g.H03K5/22- Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g.H03K5/00- Manipulating of pulses not covered by one of the other main groups of this subclass.H03M9/00- Parallel/series conversion or vice versa.
PARALLEL TO SERIAL CONVERTER BUFFER CODE
H03M- CODING DECODING CODE CONVERSION IN GENERAL.230000001276 controlling effect Effects 0.000 description 1.230000000295 complement Effects 0.000 claims description 9.
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PARALLEL TO SERIAL CONVERTER BUFFER PDF
Google Patents Parallel-to-serial converterÄownload PDF Info Publication number US5319369A US5319369A US08/093,584 US9358493A US5319369A US 5319369 A US5319369 A US 5319369A US 9358493 A US9358493 A US 9358493A US 5319369 A US5319369 A US 5319369A Authority US United States Prior art keywords parallel phase clock signal signal signals Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US5319369A - Parallel-to-serial converter US5319369A - Parallel-to-serial converter